Abstract :
In this paper, a scheme based on Verilog language to implement the high-speed and low power consumption bidirectional Viterbi decoder is proposed. Take the (2, 1, 8) decoder for example, the process of how to optimize the decoder is analyzed in detail. The simulation results of the decoder are obtained on Cadence NC Simulator, and they can be provided to Synopsys DC synthesis for ASIC design. Experiment results show that, on the one hand, by decoding in both positive direction and reverse direction, the delay of the Viterbi decoder introduced in this paper is half of the unilateralism decoder, and the decoding speed is greatly improved. On the other hand, by optimizing the area, storage space and the accessing times of memory, the cost of bidirectional decoding is largely reduced and the low power consumption is achieved at the same time
Keywords :
Viterbi decoding; hardware description languages; logic CAD; low-power electronics; ASIC design; Cadence NC Simulator; Synopsys DC synthesis; Verilog language; high-speed bidirection Viterbi decoder design; low power consumption; Application specific integrated circuits; Clocks; Convolution; Cost function; Cybernetics; Decoding; Delay; Energy consumption; Hardware design languages; Machine learning; Power engineering and energy; Viterbi algorithm; Bidirectional; High-speed; Low power consumption; Verilog HDL; Viterbi decoder;
