Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor

This paper proposes a novel modified Multi-Split LDPC decoder. In the proposed design, wires are shared to communicate not only the signs, but also the magnitudes of the messages among adjacent partitions of the LDPC codes. As a result, the proposed decoder can achieve significant coding gain over existing designs when the same word length is used. In addition, the error correcting performance of the proposed decoder is better than prior decoders even when shorter word length is adopted. Synthesis was carried out for fully-parallel decoders of an example (504, 252) LDPC code. To achieve similar performance as previous effort, the proposed decoder requires 13% hardware complexity.