Title :
A low-cost architecture for multi-mode Reed-Solomon decoder
Author :
Yun Chen ; Yuebin Huang ; Wei Meng ; Zhiyi Yu ; Xiaoyang Zeng
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
This paper presents a multi-mode Reed-Solomon (RS) decoder with folding architecture which has low cost and low power consumption. The solution can be applied into any application that requires multi-mode RS codes. Implemented by SMIC 0.13 μm 1.2 V CMOS technology, the decoder runs at 440MHz clock rate and has a gate count of 65K and die size of 1.18×1.18 mm2. The power consumption is 0.25mW per error byte benefiting from the proper mode control, which is quite economical for a multi-mode RS decoder. The maximum error correction capability of the decoder is 32 bytes.
Keywords :
Reed-Solomon codes; clocks; decoding; error correction; reduction (chemical); CMOS technology; SMIC; clock rate; frequency 440 MHz; low-cost architecture; maximum error correction capability; multimode Reed-Solomon decoder; power consumption; proper mode control; voltage 1.2 V; Clocks; Computer architecture; Decoding; Hardware; Power demand; Reed-Solomon codes; Throughput; Reed-Solomon codes; VLSI architecture; low cos; multi-mode;
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
DOI :
10.1109/ISOCC.2012.6407108
