CMOS-ASIC life-predictions from test-coupon data

Establishes the design and test requirements for test structures fabricated in test coupons and demonstrates the use of test structure data in predicting the lifetime of long-life application-specific integrated circuits (ASICs). Data acquired from three CMOS reliability hazards, i.e., metal electromigration, hot carriers, and oxide breakdown, were used to calculate the cumulative-failure time dependence of CMOS ASICs. The experimental design required that test structures be replicated enough times on a wafer so that the structures can be stressed at three stress points, thus providing failure model parameters and their statistical distributions