System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system

Virtual platform is renowned for architecture exploration and validation, early software development, hardware/software co-development of Electronic System Level (ESL) System-on-Chip (SoC) design process. In Virtual Platform System (VPS), multi-level abstraction models should be properly adopted to achieve higher simulation performance while maintaining the platform design efforts as minimal as possible. For architecture validation, cycle-accurate system-level IP models are required to produce accurate performance simulation results. However, cycle-accurate model description often results in long modeling time and cycle inaccuracy due to complex timing behavior of given IPs. Therefore, RTL co-simulation has been widely used to avoid cycle-accurate model creation in system-level design process. In this paper, we suggest the Hybrid Virtual Platform System (H-VPS) to accelerate simulation speed by adopting co-emulation scheme into VPS while keeping cycle accuracy and minimizing risk of model creation. The experimental results of co-emulation show 12-48Kcps simulation speed, which is 6-62 times faster than VPS simulation time and is enough for architecture exploration and validation.