• DocumentCode
    2899742
  • Title

    An Algorithm for Automatic Tuning of PLLs

  • Author

    Hegazi, Emad

  • Author_Institution
    Integrated Circuits Lab., Ain Shams Univ., Cairo
  • fYear
    2007
  • fDate
    27-30 May 2007
  • Firstpage
    2260
  • Lastpage
    2263
  • Abstract
    In this paper we propose a new method for the automatic tuning of PLLs with switched capacitor banks in their VCOs. The method is implemented on a 7 GHz 130-nm CMOS PLL with 5 binary control bits. Measurement results are provided and analysis of the method is illustrated.
  • Keywords
    circuit tuning; phase locked loops; switched capacitor networks; 130 nm; 7 GHz; PLL; VCO; automatic tuning; switched capacitor banks; CMOS technology; Capacitors; Circuit optimization; Frequency conversion; Phase detection; Phase frequency detector; Phase locked loops; Switches; Tuning; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-4244-0920-9
  • Electronic_ISBN
    1-4244-0921-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2007.378733
  • Filename
    4253124
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2899742