3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures

Author

Lin, Leo Jyun-Hong ; Yih-Peng Chiou

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

35

Issue

6

fYear

2014

fDate

Jun-14

Firstpage

660

Lastpage

662

Abstract

Substrate coupling in 3-D-ICs using Cu through silicon vias (TSVs) is a predicament widely documented in recent literature. Yet, discussions remain limited to the electromagnetic framework, such that a complete understanding of noise propagation and absorption is hampered. This letter thoroughly examines these phenomena in the TSVs from the integrated perspectives of semiconductor physics and electromagnetic theory and investigates the noise reduction method using the combination of p+ guard-ring and grounded TSV via 3-D device simulation.

Keywords

copper; integrated circuit modelling; integrated circuit noise; three-dimensional integrated circuits; transient analysis; 3D device simulation; 3D transient analysis; 3D-IC; Cu; TSV-induced substrate noise; absorption; electromagnetic theory; improved noise reduction method; integrated circuit modelling; noise propagation; p+ guard-ring structure; semiconductor physics; substrate coupling; through silicon vias; Capacitance; Couplings; Noise; Substrates; Threshold voltage; Through-silicon vias; Transistors; 3-D-ICs; guarding structures; guarding structures.; semiconductor physics; substrate coupling; through-silicon via (TSV); transients;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2318301

Filename

6814812