A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks

Cache attacks have been described in the literature for over a decade now. Cache attacks are performed remotely by the use of time differences observed due to cache misses and hits, or by the use of power traces either by measuring power or by monitoring the bus between the processor and the memory to monitor the cache activity. In this paper, for the first time we have implemented a fast trace driven cache attack, and incorporated this attack into a flexible framework containing extensible processor(s). This simulator is modifiable and incorporates both Tensilica´s [9] processor simulator environment along with DRAMsim, a DRAM simulator. Thus we are able to make changes to processor´s instruction set, its cache architecture, and add additional hardware units. On this framework we have implemented a hardware / software countermeasure and shown that it is difficult to differentiate the cache misses for differing encryptions. The processor with the countermeasure is 30% more energy ef ficient, 17% more power efficient and 15% faster and when compared to processor without the countermeasure. The area of the processor with the countermeasure increases by 7.6%.