Title :
A practical approach to instruction-based test generation for functional modules of VLSI processors
Author :
Hatayama, Kazumi ; Hikone, Kazunori ; Miyazaki, Takeshi ; Yamada, Hiromichi
Author_Institution :
Res. Lab., Hitachi Ltd., Ibaraki, Japan
fDate :
27 Apr-1 May 1997
Abstract :
This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach
Keywords :
VLSI; automatic test software; computer testing; integrated circuit testing; logic testing; microprocessor chips; ALPS; ALU oriented test pattern generation system; VLSI processors; constrained test generation; functional modules; functional test pattern generation; gate level faults; instruction-based test generation; Circuit faults; Circuit testing; Costs; Design for testability; Logic design; Logic testing; Sequential analysis; System testing; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.599436
