DocumentCode
2901076
Title
Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System
Author
Liu, Liang ; Ren, Junyan ; Wang, Xuejing ; Ye, Fan
Author_Institution
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
fYear
2007
fDate
27-30 May 2007
Firstpage
2594
Lastpage
2597
Abstract
A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.
Keywords
MIMO communication; OFDM modulation; digital arithmetic; fast Fourier transforms; microprocessor chips; ultra wideband communication; FFT processor; MIMO-OFDM UWB communication system; mixed radix algorithm; modified shift-add algorithm; Application specific integrated circuits; Costs; Delay; Energy consumption; Hardware; MIMO; Registers; Signal processing algorithms; Throughput; Ultra wideband communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.377846
Filename
4253208
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