Managing risk in ASIC design cycle

ASIC design validation, confirming that the chips work in the system, has been the major source of risk in any ASIC development cycle. The risk is that of missing the market window. The cause is the lack of technologies to assure, before fabrication, that ASIC designs will operate properly in the target system. Innovations in the area of field programmable gate arrays have enabled an ASIC system design tool technology called reprogrammable hardware emulation. The management of risk and the economic advantage of using this technology in the ASIC design cycle is studied