DocumentCode :
2901355
Title :
Experimental fault analysis of 1 Mb SRAM chips
Author :
Goto, Hiroyuki ; Nakamura, Shigeo ; Iwasaki, Kazuhiko
Author_Institution :
Fac. of Eng., Chiba Univ., Japan
fYear :
1997
fDate :
27 Apr-1 May 1997
Firstpage :
31
Lastpage :
36
Abstract :
Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that Idd=4.5 I; temperature=70°C, and load capacity CL=30 pF, we detected margin faults in 460 chips. Because the actual fault data for SRAM chips is rarely reported, the data in this manuscript are very useful and should be of practical importance
Keywords :
SRAM chips; fault diagnosis; integrated circuit testing; 1 Mbit; 30 pF; 70 C; SRAM chips; fault analysis; load capacity; margin fault detection; memory testing; neighborhood-pattern-sensitive faults; stuck-at bit-line faults; stuck-at cell faults; stuck-at word-line fault; Application specific integrated circuits; Cache memory; Data engineering; Decoding; Fault detection; Random access memory; SRAM chips; Temperature; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
ISSN :
1093-0167
Print_ISBN :
0-8186-7810-0
Type :
conf
DOI :
10.1109/VTEST.1997.599438
Filename :
599438
Link To Document :
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