Efficient 2DMesh Network on Chip (NoC) Considering GALS Approach

State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to scale to large systems. To solve this problem the Network on Chip (NoC) design paradigm has been introduced, where nodes communicate by exchanging packets through an interconnection network, which consists of routers and networks interfaces. The routers provide reliable data transfer. The network interfaces implement, via connections, high level services, such as transaction ordering, throughput and latency guarantees, and end-to-end flow control. In this research a 2D mesh node communication architecture of NoC is designed and simulated applying the GALS approach. A set of algorithms are also provided for these purpose.