Title :
Clock skew determination from parameter variations at chip and wafer level
Author :
Sauter, Stephan ; Cousinard, D. ; Thewes, Roland ; Schmitt-Landsiedel, D. ; Weber, Werner
Author_Institution :
Corp. Technol. Microelectron., Siemens AG, Munich, Germany
Abstract :
Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions at chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42 ps for a 0.25 μm process and a metal-3 H-clock tree
Keywords :
circuit simulation; clocks; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit measurement; integrated circuit metallisation; timing; chip level parameter variations; chip position; clock skew determination; clock skews; clock tree circuits; delay; device parameters; layout area; measured data; metal line parameters; metal-3 H-clock tree; parameter variations; power consumption; processing related fluctuation contributions; random fluctuation; simulations; temperature parameter; wafer level parameter variations; wafer position; worst case skew; Area measurement; Circuit simulation; Clocks; Delay; Energy consumption; Fluctuations; Position measurement; Power measurement; Semiconductor device measurement; Temperature;
Conference_Titel :
Statistical Metrology, 1999. IWSM. 1999 4th International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-5154-1
DOI :
10.1109/IWSTM.1999.773183
