A validation strategy for embedded core ASICs

ASIC in-circuit emulation technology for validation of embedded core ASICs in target systems is described. The emulation system contains an array of reprogrammable logic devices. Any ASIC vendor netlist can be accepted by the software. It is automatically partitioned, placed, and routed on the array of reprogrammable logic devices, called the emulation modules. The system creates a gate-by-gate, wire-by-wire replica of an ASIC design onto real hardware. In-circuit interface cables connect the functional image of the ASIC to the target system. This allows the designer to plug the ASIC design into the target system prior to having silicon built. The advantage is validation of the system design with full software and applications before actually committing to silicon. This makes design tradeoffs possible at an earlier stage. The built-in logic analyzer allows the designer to debug the ASIC design while running in-circuit, much like a microprocessor in-circuit emulator