Title :
Circuit performance variability decomposition
Author :
Orshansky, Michael ; Spanos, Costas ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
In this paper, circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into the deep sub-micron regime, the interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability
Keywords :
CMOS integrated circuits; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; timing; 0.18 micron; CMOS technology; circuit delay; circuit performance variability composition analysis; circuit performance variability decomposition; circuit variability; delay variability composition; device designs; device variability; global interconnect line variance model; interconnect; intra-field variability; overall variability; technology scaling; CMOS technology; Circuit analysis; Circuit optimization; Circuit synthesis; Delay; Design optimization; Integrated circuit interconnections; Manufacturing; Performance analysis; Semiconductor device modeling;
Conference_Titel :
Statistical Metrology, 1999. IWSM. 1999 4th International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-5154-1
DOI :
10.1109/IWSTM.1999.773184
