Title :
SPIL-a program to automatically create ASIC macro models for logic simulation
Author :
Harrington, B.K.
Author_Institution :
Siemens Components Inc., Santa Clara, CA
Abstract :
A program that automatically created emitter-coupled logic ECL and current-mode logic (CML) gate array macro models for several logic simulators is described. The program extracts the logic netlist from SPICE ECL or CML netlists, assigns timing delays supplied from external flies, optimizes the netlist and creates logic simulation models for the DAZIX´s DLS, Mentor Graphic´s QuickSim, and Zycad´s MACH 1000 logic simulators
Keywords :
application specific integrated circuits; bipolar integrated circuits; circuit layout CAD; digital integrated circuits; emitter-coupled logic; logic CAD; ASIC macro models; CML gate array macros; DAZIX´s DLS; ECL gate array macros; Mentor Graphic´s QuickSim; SPICE logic extraction program; SPIL; Zycad´s MACH 1000 logic simulators; current-mode logic; emitter-coupled logic; gate array macro models; logic netlist extraction; logic simulation; logic simulation models; logic simulators; macro models automatic creation; netlist optimisation; timing delays assignment; Application specific integrated circuits; Automatic logic units; Circuit simulation; Computational modeling; Computer simulation; Delay; Integrated circuit modeling; Logic circuits; Resistors; Timing;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186121
