DocumentCode
2901857
Title
Implicit test pattern generation constrained to cellular automata embedding
Author
Fummi, F. ; Sciuto, D.
Author_Institution
Dipt. di Elettronica, Politecnico di Milano, Italy
fYear
1997
fDate
27 Apr-1 May 1997
Firstpage
54
Lastpage
59
Abstract
This paper presents an implicit methodology that constrains a test pattern generator to identify test sequences which can be reproduced by cellular automata (CA). The so identified CA can be synthesized as an autonomous finite state machine and can be attached to the inputs of a circuit under test (e.g., a controller). In this way, the circuit under test preserves its integrity and its performance is not affected by the proposed testing technique. The overall device (controller+CA) is an off-line self-testable circuit which con potentially self-test all stuck-at faults both of the controller and the CA. Thus, the method can be viewed as a BIST strategy based on the embedding of deterministic test sequences
Keywords
application specific integrated circuits; built-in self test; cellular automata; deterministic automata; fault diagnosis; finite state machines; integrated circuit testing; logic testing; sequential circuits; ASIC design; BIST strategy; MCNC benchmarks; autonomous finite state machine; cellular automata embedding; circuit under test; controller; deterministic test sequences; implicit test pattern generation; off-line self-testable circuit; stuck-at faults; test sequence identification; Automatic control; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Sequential analysis; Space exploration; Telecommunication control; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-7810-0
Type
conf
DOI
10.1109/VTEST.1997.599441
Filename
599441
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