Title :
Design trade-offs when implementing boundary scan in an application specific integrated circuit
Author :
Moxon, Thomas W.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
The design tradeoffs encountered when implementing a ASIC design that incorporates boundary scan logic are discussed. Boundary scan logic can improve both the device- and system-level testability. The designer, however, must weigh the impact on silicon area, performance, routability, and implementation time to achieve the optimum design solution
Keywords :
VLSI; application specific integrated circuits; built-in self test; digital integrated circuits; ASIC design; BIST; Si area impact; application specific integrated circuit; boundary scan; boundary scan logic; design for testability; design tradeoffs; device-level testability; implementation time; optimum design solution; performance; routability; system-level testability; Application specific integrated circuits; Built-in self-test; Integrated circuit technology; Libraries; Logic design; Logic devices; Logic testing; System testing; Technology management; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186153
