DocumentCode
2902036
Title
Design trade-offs when implementing boundary scan in an application specific integrated circuit
Author
Moxon, Thomas W.
Author_Institution
VLSI Technol. Inc., San Jose, CA, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
The design tradeoffs encountered when implementing a ASIC design that incorporates boundary scan logic are discussed. Boundary scan logic can improve both the device- and system-level testability. The designer, however, must weigh the impact on silicon area, performance, routability, and implementation time to achieve the optimum design solution
Keywords
VLSI; application specific integrated circuits; built-in self test; digital integrated circuits; ASIC design; BIST; Si area impact; application specific integrated circuit; boundary scan; boundary scan logic; design for testability; design tradeoffs; device-level testability; implementation time; optimum design solution; performance; routability; system-level testability; Application specific integrated circuits; Built-in self-test; Integrated circuit technology; Libraries; Logic design; Logic devices; Logic testing; System testing; Technology management; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186153
Filename
186153
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