Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Many critical design trade-offs of the class-E power amplifier (e.g power efficiency) are influenced by the switch on-resistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the class-E power amplifier with finite dc-feed inductance assume zero switch on-resistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs. We present analytical design equations in this paper for class-E power amplifier taking into account both finite drain inductance and switch on-resistance. The analysis indicates the existence of infinitely many design equations; conclusions include: 1) class-E conditions (e.g. zero voltage and zero slope) can be satisfied in the presence of switch-on resistance. 2) The drain-efficiency (eta) of the class-E power amplifier is upper limited for a certain operation frequency and transistor technology. 3) Using a finite dc-feed inductance instead of an RF-choke in a class-E power amplifier can increase eta by ap 30%.