Title :
Reliability, testability and yield of majority voting VLSI
Author :
Stroud, Charles E. ; Barbour, Ahmed E.
Author_Institution :
AT&T Bell Lab., Naperville, IL, USA
Abstract :
Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved
Keywords :
VLSI; circuit reliability; integrated circuit testing; integrated logic circuits; logic design; logic testing; VLSI designs; defect tolerance; fault tolerance; logic circuits; majority voting VLSI; reliability; testability; Circuit faults; Circuit simulation; Circuit testing; Complexity theory; Nuclear magnetic resonance; Routing; Very large scale integration; Voting;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186155
