Title :
Design and test strategy for differential cascode voltage switch circuits
Author :
Wu, D.M. ; Davis, J.W. ; Thoma, N.G.
Author_Institution :
IBM VLSI Silicon, Boca Raton, FL, USA
Abstract :
A test methodology for the differential cascode voltage switch (DCVS) is described. The design methodology of DCVS makes it more testable compared to other technologies. In testing DCVS, a precharge state always precedes a test pattern or a functional pattern. This test methodology permits detection of delay faults and stuck-open faults. The good circuit outputs of a logic tree are orthogonal. A high percentage of defects can be detected through the XOR gate designed for testing nonorthogonal faults
Keywords :
fault location; logic design; logic testing; DCVS; XOR gate; delay faults; design methodology; differential cascode voltage switch circuits; functional pattern; nonorthogonal faults; precharge state; stuck-open faults; test pattern; test strategy; Automatic testing; Circuit faults; Circuit testing; Fault detection; Integrated circuit interconnections; Latches; Logic testing; Switches; Switching circuits; Voltage;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186156
