Development of an ASIC macrocell design CAD system

An important factor in bringing a new product to market for a successful ASIC business is the generation of design data related to macrocells, such as graphic symbols, logic simulation models, input-to-output path delays, and timing parameters for the ASIC CAD system so that ASIC customers can begin designing with the new ASIC product. Logic model generation, transition from logic to circuit simulation, circuit design with estimated parasitics, circuit verification of physical layout, and encapsulation of the macrocell design CAD flow are considered