An automated, structured layout methodology for staggered pad, I/O-bound ASIC design

Author

Lu, Luke Y. ; Alston, Michael D.

Author_Institution

Silicon Connections Corp., San Diego, CA, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

A design methodology developed and implemented for high-pin-count cell-based BiCMOS ASIC designs is discussed. Described is the orchestration of different vendors´ CAD tools via tool-specific shell scripts, macros, file reformatting/conversion software and application software to methodically place and route I/O pad cells, I/O circuit cells, and core logic megacells, rapidly completing the correct-by-construction layout of a staggered-pad, I/O-bound ASIC

Keywords

BIMOS integrated circuits; application specific integrated circuits; circuit layout CAD; CAD tools; I/O circuit cells; I/O pad cells; I/O-bound ASIC design; application software; automated design; cell-based BiCMOS; conversion software; core logic megacells; correct-by-construction layout; design methodology; file reformatting; high-pin-count; macros; placement; routeing; staggered pad; structured layout methodology; tool-specific shell scripts; Application specific integrated circuits; Atherosclerosis; BiCMOS integrated circuits; Design automation; Design methodology; Logic circuits; Logic design; Shape; Silicon; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186167

Filename

186167