Title :
Behavioral models of ASIC VLSI cells
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
Behavioral models, while more difficult to produce than gate-level models, provide invaluable features during the design verification process. These models exhibit timing and functional accuracy, while providing significantly increased performance and debug features. Techniques to decrease the effort required to produce behavioral models of ASIC VLSI cells are discussed. Behavioral models of ASIC VLSI cells can greatly decrease the time required to verify a design
Keywords :
VLSI; application specific integrated circuits; circuit CAD; semiconductor device models; ASIC VLSI cells; behavioral models; debug features; design verification process; Accuracy; Application specific integrated circuits; Circuit simulation; Delay estimation; Microcomputers; Propagation delay; Temperature; Timing; Very large scale integration; Voltage;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186170
