Title :
Design methodology for a 1.0 μ cell-based library efficiently optimized for speed and area
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
The CHMOS IV ASIC 1.0 μ cell-based library avoids area and performance penalties by using a design methodology that specifically addresses cell efficiency. The library was successfully optimized for speed, cell density, chip density, and noise immunity. It is useful for both the ASIC and the internal design communities. The internal design community will adopt only those libraries which push performance to the limit. ASIC users can enjoy the performance advantages without sacrificing chip density. Having a single library that is useful for both internal and external purposes saves time and valuable resources
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit CAD; circuit layout CAD; 1 micron; ASIC; CAD; CHMOS IV; cell density; cell efficiency; cell-based library; chip density; design methodology; noise immunity; speed optimisation; Application specific integrated circuits; Delay; Design methodology; Design optimization; Libraries; Logic; Routing; Signal to noise ratio; Variable structure systems; Voltage;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186171
