Interfacing test equipment to high density chip-on-tape

Author

Nelson, Randy ; Williams, Bill ; Westbrook, Greg

Author_Institution

Motorola ASIC Div., Chandler, AZ, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

Test hardware interface requirements for testing high-pin-count ASIC TAB (tape automated bonding) products are discussed. Test solutions which have been proven in a production environment are described. Test-on-tape using the techniques illustrated has proven viable for high-speed bipolar gate arrays having 360 leads with 0.004 in lead width and 0.008 in lead pitch in the (outer lead bond) and test area. Successfully testing small pitch outer leads of TAB products requires the combination of electrical, mechanical, and thermal designs to be controlled within specific tolerances. The final testing of TAB ASICs is performed after all other value added processes have been completed. Therefore, an understanding of the factors which impact final test yield is essential

Keywords

application specific integrated circuits; integrated circuit testing; production testing; tape automated bonding; test equipment; ASIC; TAB products; high density chip-on-tape; high-pin-count; high-speed bipolar gate arrays; production environment; small pitch outer leads; tape automated bonding; test equipment; test hardware interfacing; Application specific integrated circuits; Automatic testing; Circuit testing; Hardware; Impedance; Integrated circuit testing; Software testing; System testing; Test equipment; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186178

Filename

186178