DocumentCode
2902587
Title
An Intel 18253 ASIC chip design
Author
Hsieh, Yu-I
Author_Institution
Sharp Microelectron. Technol. Inc., Camas, WA, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
The establishment of the engineering rules to create the executable and synthesizable (and/or testable) specification for an ASIC design in an ASIC CAD environment is discussed. The Intel 8253 programmable timer/counter was selected as a test example to illustrate the strengths and weaknesses of this CAD technology. The need for a high-performance cell-based ASIC/IC CAD system is critical for this application
Keywords
application specific integrated circuits; circuit CAD; counting circuits; timing circuits; CAD environment; Intel 18253 ASIC chip design; cell-based ASIC/IC CAD system; engineering rules; programmable timer/counter; Application specific integrated circuits; Automatic test pattern generation; Chip scale packaging; Clocks; Design automation; Hardware design languages; Libraries; Logic; Synthesizers; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186189
Filename
186189
Link To Document