Title :
Tunnel FET-based pass-transistor logic for ultra-low-power applications
Author :
Kim, Sung Hwan ; Jacobson, Zachery A. ; Patel, Pratik ; Hu, Chenming ; Liu, Tsu-Jae King
Author_Institution :
EECS Dept., Univ. of California, Berkeley, CA, USA
Abstract :
Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>;100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.
Keywords :
CMOS logic circuits; elemental semiconductors; field effect logic circuits; germanium; logic gates; low-power electronics; Ge; conventional CMOS logic gates; dynamic energy; germanium-source tunnel-FET-based pass-transistor logic gates; leakage power; mixed-mode simulations; size 15 nm; ultra-low-power applications; CMOS integrated circuits; Logic gates; MOSFET circuits;
Conference_Titel :
Device Research Conference (DRC), 2011 69th Annual
Conference_Location :
Santa Barbara, CA
Print_ISBN :
978-1-61284-243-1
Electronic_ISBN :
1548-3770
DOI :
10.1109/DRC.2011.5994452
