Title :
Economic implications of logic synthesis
Author :
Grimblatt-Hinzpeter, V. ; Morrison, Christopher R. ; Finley, R. Scott
Author_Institution :
VLSI Technol., Valbonne, France
Abstract :
An overview of logic synthesis and the different methodologies used in the tools realizing synthesis is presented. The objective is to show the economic implications of synthesis (performance and area of the chip, design time, silicon costs, etc.). The mainstream methodology used in synthesis tools and the possible applications are presented. Future methodologies and some ideas for the reduction of chip costs using the existing tools and possible future tools are discussed
Keywords :
economics; logic design; area; chip costs; design time; economic implications; logic synthesis; silicon costs; Circuit simulation; Circuit synthesis; Costs; Encoding; Equations; Fabrication; Hardware design languages; Logic; Silicon; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186206
