Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

This paper presents a new 32-bit adder structure with 12 GHz low-power operation in 65nm technology. The fast conditional sparse-tree logic (FCSL) is based on modifying the initial sparse-tree architecture (Mathew et al., 2003) to enhance its speed using tertiary trees and applying a carry-select scheme in some of the more significant bits. This design has been compared with the sparse-tree adder and the low-voltage swing adder in terms of speed and power. It has been shown that speed can be improved using FCSL architecture while keeping the power at a comparable level.