A novel VLSI array design for the discrete Hartley transform using cyclic convolution

This paper presents a novel VLSI array design for the 1-D discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, we develop an algorithm which can formulate the 1-D any-length DHT as cyclic convolutions. This algorithm owns higher flexibility in the transform length as compared with the existing approach of Guo, Liu, and Jen (see Proc. IEEE International Conference on Acoustics; Speech, and Signal Processing, p.v.621-v.624, 1992 and IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.30, p.723-733, Oct. 1992). Moreover, we use the memory-based approach to realize the cyclic convolutions by systolic arrays and implement the multiplications by small ROMs and adders. The presented array not only outperforms the distributed arithmetic (DA) architectures in the hardware area, but also owns low input/output (I/O) cost, power dissipation, high computing speeds and flexibility in transform length