On the formal derivation of a systolic array for recursive least squares estimation

A formal proof is presented, for the first time, for a recently developed systolic array for recursive least squares estimation proposed by Moonen and McWhirter (see Electronics Letters, 1993). The derivation of this array is non-trivial due to the presence of feedback loops and data contra-flow in the underlying signal flow graph (SFG). This would normally prohibit pipelined processing. However, it is shown that suitable delays may be introduced to the SFG by performing simple algorithmic transformations which compensate for the interference of crossing data flows and eliminate the critical feedback loops. The pipelined systolic array is then obtained either by 2-slowing and retiming the SFG or by means of dependence graph scheduling and assignment