DocumentCode :
2903337
Title :
A Scan Chain Adjustment Technology for Test Power Reduction
Author :
Li, Jia ; Hu, Yu ; Li, Xiaowei
Author_Institution :
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing
fYear :
2006
fDate :
Nov. 2006
Firstpage :
11
Lastpage :
16
Abstract :
Recently test power dissipation has become a more and more challenging issue. This paper proposes a technique to solve this problem through scan chain adjustment to eliminate unnecessary transitions in scan chains. An extended WTM (EWTM) metric is proposed to estimate dynamic power dissipation in circuit under test caused by transitions in test stimulus and response vectors. And the routing overhead of this methodology can be reduced through scan chain adjustment guided with our distance of EWTM (DEWTM) metric. Experimental results on ISCAS´89 benchmarks circuits show that the proposed approach can reduce average power dissipation during scan test by 72.2% on average, with negligible routing overhead
Keywords :
boundary scan testing; logic testing; system-on-chip; circuit under test; dynamic power dissipation; extended weighted transform metric; routing overhead; scan chain adjustment; scan test; test power reduction; Benchmark testing; Circuit testing; Computers; Content addressable storage; Laboratories; Power dissipation; Power engineering and energy; Routing; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
ISSN :
1081-7735
Print_ISBN :
0-7695-2628-4
Type :
conf
DOI :
10.1109/ATS.2006.260986
Filename :
4030734
Link To Document :
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