• DocumentCode
    2903359
  • Title

    Challenges for post-CMOS devices & architectures

  • Author

    Welser, J. ; Bernstein, K.

  • Author_Institution
    SRC-NRI, Durham, NC, USA
  • fYear
    2011
  • fDate
    20-22 June 2011
  • Firstpage
    183
  • Lastpage
    186
  • Abstract
    Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. NRI seeks to find not just a one generation improvement on the FET, but rather a new extended scaling path. This is crucial to justify the expense of making any major change in the current technology infrastructure (both at the device and design level) - and the larger the change, the more benefit and longevity the new technology must offer.
  • Keywords
    CMOS integrated circuits; field effect transistors; CMOS FET; Nanoelectronics Research Initiative; information technology; logic switch; post-CMOS devices; semiconductor industry; CMOS integrated circuits; Heterojunctions; Magnetic tunneling; Nanowires; Silicon; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference (DRC), 2011 69th Annual
  • Conference_Location
    Santa Barbara, CA
  • ISSN
    1548-3770
  • Print_ISBN
    978-1-61284-243-1
  • Electronic_ISBN
    1548-3770
  • Type

    conf

  • DOI
    10.1109/DRC.2011.5994480
  • Filename
    5994480