Cu low k device wire bonding process modeling

As semiconductor industry reaches 90 nm technology node and below, Cu low k technology has been widely used in integrated circuits to further reduce RC delay and power dissipation. Due to the intrinsic properties of low K material (poor adhesion with metal layer, lower modulus and higher CTE), wire bond process window gets narrowed. Crack/peeling between low k ILD layer and metal (barrier) layer are common wire bond defects which cause both packaging manufacturability and product reliability issues. In this paper, physical and mathematical models of wire bonding process were established. The regression equation of impact force and C/V (contact velocity) was obtained through simulation and actual wire bonding data. A Cu low k CMOS 90 nm test vehicle was chosen for the modeling. The bonding impact load curve was obtained through the regression of modeling and actual bonding response. The effect of impact force on the formation of smashed ball as well as the mechanical deformation imposed to the bond pad was studied. Through simulation, capillary dimension - ICA (inner chamfer angle) was found critical to achieve 25% BBR (ball height to ball size ratio) with 40 um BPO (bond pad opening) which is important for consistent IMC formation and stronger IMC integrity over heat excursion. Through the bond pad deformation simulation under different metal structure design, it is found local low K dielectric design can effectively reduce the bond pad deformation & cupping, thus widen the wire bond process window.