DocumentCode :
2903585
Title :
Performance-sensitivity and performance-similarity based workload reduction
Author :
Jie Luo ; Morales, K. ; Byeong Kil Lee ; John, Eugene ; Young Kyu Choi
Author_Institution :
Univ. of Texas at San Antonio, San Antonio, TX, USA
fYear :
2012
fDate :
1-3 Dec. 2012
Firstpage :
21
Lastpage :
30
Abstract :
In computer design area, pre-silicon early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite takes several weeks to several months. Among many techniques for reducing simulation time, a tool called SimPoint is popularly used. Even though, simulation load with the reduced workloads by SimPoint is still heavy considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis for workload reduction by using statistical technique. Our experiment results show that the proposed scheme provides around 50% reduction with 0.2%-3.5% error rate over original SimPoint method.
Keywords :
benchmark testing; integrated circuit design; microprocessor chips; performance evaluation; SimPoint; architectural behaviors; computer design area; configuration changes; cycle-level microprocessor simulator; design complexity; industry standard benchmark suite; optimal configurations; performance-sensitivity based workload reduction; performance-similarity based workload reduction; pre silicon early-stage design exploration; resource variations; simulation load; simulation point; simulation time reduction; simulation-level design exploration; Benchmark testing; Hardware; Hidden Markov models; Mathematical model; Sensitivity; Standards; early-stage design exploration; performance evaluation; workload characterization; workload reduction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Computing and Communications Conference (IPCCC), 2012 IEEE 31st International
Conference_Location :
Austin, TX
ISSN :
1097-2641
Print_ISBN :
978-1-4673-4881-2
Type :
conf
DOI :
10.1109/PCCC.2012.6407717
Filename :
6407717
Link To Document :
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