Title :
How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes
Author :
Wong, Paul ; Jiang, Jing
Author_Institution :
Rambus Inc., Los Altos, CA
Abstract :
Modern day mixed-signal designs present interesting challenges to DFT timing flow. In this paper, we will discuss how we devised a DFT timing flow utilizing dynamic simulation with a turn around time better than that of a STA tool. In particular, we describe a design where run time has been reduced from 28 hours to 7 minutes
Keywords :
design for testability; integrated circuit design; mixed analogue-digital integrated circuits; 28 hours; 7 mins; DFT timing; STA tool; dynamic simulation; mixed signal designs; run time; Circuit simulation; Clocks; Debugging; Design for testability; Driver circuits; Graphics; Hardware design languages; Signal design; Testing; Timing;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.261004
