Title :
Mentor Graphics DFT to Navigate Nanometer Test Challenges
Author :
Aldrich, Greg ; Press, Ron ; Kobayashi, Takeo ; Sakajiri, Tatsuo
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
Abstract :
Nanometer designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries. Semiconductor companies creating these nanometer designs are struggling with many issues that result from this shrinking complex design environment. Mentor graphics design-for-test is committed to helping you navigate these challenges to bringing a high quality product to market while reducing test cost
Keywords :
cost reduction; design for testability; nanotechnology; DFT; complex design; high quality product; nanometer test; test cost reduction; Automatic test pattern generation; Costs; Design for testability; Fault detection; Geometry; Graphics; Navigation; Semiconductor device testing; System testing; Time to market;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.261008
