• DocumentCode
    2903778
  • Title

    The Application of BIST-Aided Scan Test for Real Chips

  • Author

    Konishi, Hideaki ; Emori, Michiaki ; Hiraide, Takahisa

  • Author_Institution
    Fujitsu Ltd., Kawasaki
  • fYear
    2006
  • fDate
    Nov. 2006
  • Firstpage
    131
  • Lastpage
    131
  • Abstract
    It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact
  • Keywords
    automatic test pattern generation; built-in self test; large scale integration; logic testing; ATPG; BIST-aided scan test; LSI testing; design complexity; real chips; scan-based design; test cost; Automatic test pattern generation; Chip scale packaging; Circuit faults; Circuit testing; Costs; Design for testability; Hardware; Large scale integration; Logic testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2006. ATS '06. 15th Asian
  • Conference_Location
    Fukuoka
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2628-4
  • Type

    conf

  • DOI
    10.1109/ATS.2006.261009
  • Filename
    4030757
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2903778