Title :
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs
Author :
Uzzaman, Anis ; Keller, Brion ; Chickermane, Vivek
Author_Institution :
Cadence Design Syst., Inc., Endicott, NY
Abstract :
This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results
Keywords :
data compression; integrated circuit design; system-on-chip; design flow; on-chip compression; scalable architecture; test data compression; Automatic test pattern generation; Built-in self-test; Costs; Data compression; Delay; Logic testing; Silicon; System testing; System-on-a-chip; Test data compression;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.261010
