DocumentCode
2903902
Title
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits
Author
Agrawal, Pulin ; Agrawal, Vishwani D.
Author_Institution
AT&T Bell Laboratories
fYear
1992
fDate
4-7 Jan 1992
Firstpage
4
Lastpage
11
Keywords
Circuit faults; Circuit testing; Delay effects; Flip-flops; Logic testing; Propagation delay; Robustness; Sequential analysis; Sequential circuits; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1992. Proceedings., The Fifth International Conference on
ISSN
1063-9667
Print_ISBN
0-8186-2465-5
Type
conf
DOI
10.1109/ICVD.1992.658013
Filename
658013
Link To Document