• DocumentCode
    2903993
  • Title

    ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

  • Author

    Karimi, Naghmeh ; Mirkhani, Shahrzad ; Navabi, Zainalabedin

  • Author_Institution
    Electr. & Comput. Eng. Dept., Tehran Univ.
  • fYear
    2006
  • fDate
    20-23 Nov. 2006
  • Firstpage
    195
  • Lastpage
    202
  • Abstract
    This paper proposes a novel and efficient method for RT level online testing. Our method makes every RT-level resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or latency overhead are due to concurrent operation of active and inactive resources. This method is evaluated by fault simulating several benchmark designs before and after applying the proposed algorithm. Experimental results show that after applying our method, online fault coverage is significantly improved
  • Keywords
    fault simulation; integrated circuit reliability; integrated circuit testing; logic testing; ESTA method; RT level online testing; RT-level designs; area overhead; dead intervals; fault simulation; latency overhead; online fault coverage; reliability enhancement; stuck-at fault detection; Circuit faults; Circuit testing; Delay; Design engineering; Electrical fault detection; Error correction codes; Hardware; Reliability engineering; Sequential circuits; Voting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2006. ATS '06. 15th Asian
  • Conference_Location
    Fukuoka
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2628-4
  • Type

    conf

  • DOI
    10.1109/ATS.2006.261020
  • Filename
    4030768