Title :
A Cost Effective Output Response Analyzer for sum - delta Modulation Based BIST Systems
Author :
Hong, Hao-Chiao ; Liang, Sheng-Chuan
Author_Institution :
Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsin-Chu
Abstract :
A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications
Keywords :
built-in self test; circuit testing; sigma-delta modulation; BIST systems; CPU; DSP; Sigma-Delta modulation; bulky memory; circuit under test; fast Fourier transform; modified controlled sine wave fitting; output response analyzer; parallel multiplier; second-order design-for-digital-testability; signal power calculation; signal-to-noise-and-distortion ratio; standard deviation; total-harmonic-distortion-and-noise power; Analytical models; Built-in self-test; Circuit simulation; Circuit testing; Costs; Delta modulation; Delta-sigma modulation; Digital signal processing; Fast Fourier transforms; Frequency domain analysis;
Conference_Titel :
Test Symposium, 2006. ATS '06. 15th Asian
Conference_Location :
Fukuoka
Print_ISBN :
0-7695-2628-4
DOI :
10.1109/ATS.2006.261029