A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

Author

Huang, Jiun-Lang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2006

fDate

20-23 Nov. 2006

Firstpage

318

Lastpage

326

Abstract

In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for on-chip jitter tolerance testing applications. First, the period-tracking technique (Kuo and Huang, 2006) is utilized to derive the SJ frequency and amplitude information. Then, using the same design-for-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique

Keywords

design for testability; integrated circuit noise; integrated circuit testing; jitter; tolerance analysis; binary search; design-for-test circuit; on-chip jitter tolerance testing; period-tracking; random jitter extraction; sigma value; sinusoidal jitter; Circuit testing; Data mining; Delay lines; Design for testability; Digital signal processing; Electronic equipment testing; Frequency; Jitter; Sampling methods; Time measurement; built-in self-test.; design-for-test; jitter decomposition; jitter tolerance; random jitter; sinusoidal jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2006. ATS '06. 15th Asian

Conference_Location

Fukuoka

ISSN

1081-7735

Print_ISBN

0-7695-2628-4

Type

conf

DOI

10.1109/ATS.2006.260950

Filename

4030786