• DocumentCode
    2904364
  • Title

    An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time

  • Author

    Wang, Zhanglei ; Chakrabarty, Krishnendu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC
  • fYear
    2006
  • fDate
    Nov. 2006
  • Firstpage
    333
  • Lastpage
    338
  • Abstract
    Testing using n-detection test sets, in which a fault is detected by n (n > 1) input patterns, is being increasingly advocated to increase defect coverage. However, the data volume for an n-detection test set is often too large, resulting in high testing time and tester memory requirements. Test set selection is necessary to ensure that the most effective patterns are chosen from large test sets in a high-volume production testing environment. Test selection is also useful in a time-constrained wafer-sort environment. The authors use a probabilistic fault model and the theory of output deviations for test set selection - the metric of output deviation is used to rank candidate test patterns without resorting to fault grading. To demonstrate the quality of the selected patterns, experimental results were presented for resistive bridging faults and non-feedback zero-resistance bridging faults in the ISCAS benchmark circuits. Our results show that for the same test length, patterns selected on the basis of output deviations are more effective than patterns selected using several other methods
  • Keywords
    automatic test pattern generation; fault simulation; integrated circuit testing; ISCAS benchmark; defect coverage; nonfeedback zero-resistance bridging; output deviations; probabilistic fault model; reduced test data; resistive bridging faults; test application time; test pattern selection; test set selection; Application software; Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit interconnections; Integrated circuit modeling; Production; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2006. ATS '06. 15th Asian
  • Conference_Location
    Fukuoka
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2628-4
  • Type

    conf

  • DOI
    10.1109/ATS.2006.260952
  • Filename
    4030788