Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology

Author

Foutz, Brian ; Chickermane, Vivek ; Li, Bing ; Linzer, Harry ; Kunselman, Gary

fYear

2006

fDate

Nov. 2006

Firstpage

381

Lastpage

388

Abstract

This paper describes an automated methodology to insert IEEE 1149.6 boundary scan in a production ASIC environment. The methodology includes updating the ASIC library to support the new test receiver component, updating the TAP controller logic and boundary cells, and finally providing support for embedded high speed I/O logic. Results from several industrial designs and example circuits are shown. These examples include multi-GHz serial I/O such as those used with serial ATA and PCI-Express

Keywords

IEEE standards; application specific integrated circuits; boundary scan testing; embedded systems; logic testing; ASIC library; ASIC methodology; IEEE 1149.6; PCI-Express; TAP controller logic; boundary cells; boundary scan synthesis; embedded I/O logic; high speed I/O logic; multiGHz serial I/O; production ASIC environment; serial ATA; test receiver component; Application specific integrated circuits; Automatic testing; Automation; Circuit testing; Clocks; Firewire; Hysteresis; Libraries; Logic testing; Pins;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2006. ATS '06. 15th Asian

Conference_Location

Fukuoka

ISSN

1081-7735

Print_ISBN

0-7695-2628-4

Type

conf

DOI

10.1109/ATS.2006.260959

Filename

4030795

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2904526