2904810

An Effective Timing-Driven Placement Algorithm For Macro Cells

Wu, Ching-Ting ; Lim, Andrew ; Du, David

Univ. of Minnesota

1992

4-7 Jan 1992

31

36

Circuit optimization; Clocks; Computer science; Delay effects; Delay estimation; Integrated circuit interconnections; Routing; Timing; Very large scale integration; Wire;

English

ieee

VLSI Design, 1992. Proceedings., The Fifth International Conference on

1063-9667

0-8186-2465-5

conf

10.1109/ICVD.1992.658017

658017