Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 μm

Reconfigurable logic is gaining importance in the context of embedded systems. But cost-efficient architectures implementable in standard CMOS technology, and mature design and mapping tools for them are still missing. This paper presents a novel architecture of an embedded reconfigurable logic (RL) core optimised for DSP applications. Tuning towards the application domain allowed one to reduce the logic cell implementation cost and the logic cell routing resources by 23% and 28%, respectively, compared to a commercial FPGA device with equivalent functionality. A tile-based approach which enabled the implementation of the RL core at a reduced design effort is also described. Finally, some VLSI implementation details of the core and the test chip realised in a standard 0.13 μm CMOS process technology are discussed.