Title :
Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits
Author_Institution :
Dept. of Electr. & Electron. Eng., Shizuoka Inst. of Sci. & Technol., Fukuroi, Japan
Abstract :
Single event transient (SET) effects on cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. CVSL and CMOS chain circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS process. Both circuits have been confirmed to function correctly by the fabricated chip measurements. SET simulation results have confirmed that the CVSL circuits have increased tolerance to SET. SET tolerance for the CVSL EX-OR is compared to that for the conventional CMOS EX-OR, showing that the CVSL is a candidate for a SET tolerant spaceborne logic circuit.
Keywords :
CMOS logic circuits; SPICE; cascade networks; logic circuits; transients; CMOS ex-OR circuit; CMOS exclusive-OR circuit; CVSL ex-OR circuit; SET effect; SPICE; cascade voltage switch logic exclusive-OR circuit; double polysilicon double metal N-well CMOS process; fabricated chip measurement; single event transient effect; spaceborne logic circuit; CMOS integrated circuits; Integrated circuit modeling; Layout; Logic gates; SPICE; Semiconductor device modeling; Simulation;
Conference_Titel :
Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on
Conference_Location :
Bruges
Print_ISBN :
978-1-4577-0492-5
Electronic_ISBN :
0379-6566
DOI :
10.1109/RADECS.2009.5994567
